The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2023

Filed:

Jun. 15, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Chang-Ming Wu, New Taipei, TW;

Wei Cheng Wu, Zhubei, TW;

Shih-Chang Liu, Alian Township, TW;

Harry-Hak-Lay Chuang, Zhubei, TW;

Chia-Shiung Tsai, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 27/11521 (2017.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 29/792 (2006.01); H01L 27/1157 (2017.01); H01L 27/11524 (2017.01); H01L 27/11568 (2017.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42344 (2013.01); H01L 27/1157 (2013.01); H01L 27/11521 (2013.01); H01L 27/11524 (2013.01); H01L 27/11568 (2013.01); H01L 29/40114 (2019.08); H01L 29/40117 (2019.08); H01L 29/42324 (2013.01); H01L 29/42348 (2013.01); H01L 29/518 (2013.01); H01L 29/6653 (2013.01); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01);
Abstract

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a source/drain region arranged within a substrate. A first select gate is arranged over the substrate, and a first memory gate is arranged over the substrate and separated from the source/drain region by the first select gate. An inter-gate dielectric structure is arranged between the first memory gate and the first select gate. The inter-gate dielectric structure extends under the first memory gate. A height of the inter-gate dielectric structure decreases along a direction extending from the first select gate to the first memory gate.


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