The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2023

Filed:

Jan. 12, 2021
Applicant:

Semiconductor Components Industries, Llc, Phoenix, AZ (US);

Inventors:

Kevin Kyuheon Cho, Bucheon-si, KR;

Bongyong Lee, Seoul, KR;

Kyeongseok Park, Bucheon, KR;

Doojin Choi, Gimpo-si, KR;

Thomas Neyer, Munich, DE;

Ki Min Kim, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/78 (2006.01); H01L 29/16 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1608 (2013.01); H01L 29/1045 (2013.01); H01L 29/66068 (2013.01); H01L 29/66712 (2013.01); H01L 29/7802 (2013.01);
Abstract

A SiC MOSFET device with alternating p-well widths, including an undulating channel, is described. The undulating channel provides current paths of multiple widths, which enables optimization of on-resistance, transconductance, threshold voltage, and channel length. The multi-width p-well region further defines corresponding multi-width Junction FETs (JFETs). The multi-width JFETs enable improved response to a short-circuit event. A high breakdown voltage is obtained by distributing a high electric field in a JFET of a first width into a JFET of a second width.


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