The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2023

Filed:

Sep. 28, 2020
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Zaichen Chen, Champaign, IL (US);

Akram A. Salman, Plano, TX (US);

Binghua Hu, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/00 (2006.01); H01L 27/02 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 21/265 (2006.01); H01L 29/06 (2006.01); H01L 29/732 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 21/321 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0259 (2013.01); H01L 21/26513 (2013.01); H01L 21/76224 (2013.01); H01L 29/0649 (2013.01); H01L 29/0804 (2013.01); H01L 29/0821 (2013.01); H01L 29/1004 (2013.01); H01L 29/66234 (2013.01); H01L 29/732 (2013.01); H01L 21/02532 (2013.01); H01L 21/02579 (2013.01); H01L 21/02595 (2013.01); H01L 21/3212 (2013.01); H01L 21/76877 (2013.01);
Abstract

An electronic device includes a substrate having a second conductivity type including a semiconductor surface layer with a buried layer (BL) having a first conductivity type. In the semiconductor surface layer is a first doped region (e.g., collector) and a second doped region (e.g., emitter) both having the first conductivity type, with a third doped region (e.g., a base) having the second conductivity type within the second doped region, wherein the first doped region extends below and lateral to the third doped region. At least one row of deep trench (DT) isolation islands are within the first doped region each including a dielectric liner extending along a trench sidewall from the semiconductor surface layer to the BL with an associated deep doped region extending from the semiconductor surface layer to the BL. The deep doped regions can merge forming a merged deep doped region that spans the DT islands.


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