The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2023

Filed:

Aug. 27, 2021
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Kallol Mazumder, Dallas, TX (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01); G11C 11/4076 (2006.01); G06F 1/3234 (2019.01); H03L 7/081 (2006.01); G11C 11/4096 (2006.01); G11C 11/4093 (2006.01); G06F 1/3296 (2019.01);
U.S. Cl.
CPC ...
G11C 11/4076 (2013.01); G06F 1/3275 (2013.01); G06F 1/3296 (2013.01); G11C 11/4093 (2013.01); G11C 11/4096 (2013.01); H03L 7/0814 (2013.01); G11C 7/222 (2013.01);
Abstract

A memory device includes a command interface configured to receive a command from a host device. The memory device also includes a command shifter configured to receive the command. The command shifter includes a plurality of stages coupled in series and configured to delay the command. The command shifter comprises selection circuitry configured to receive the command and to select an insertion stage of the plurality of stages for the command. The selection circuitry is configured to select the insertion stage as a location to insert the command. The selected insertion stage is selected to control a duration of delay in the command shifter. The selection of the insertion stage is based at least in part on a path delay between a clock and a data pin of the memory device.


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