The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2023

Filed:

Oct. 11, 2021
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Toru Tanzawa, Adachi, JP;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/027 (2006.01); H01L 27/11582 (2017.01); H01L 27/11524 (2017.01); H01L 27/11531 (2017.01); H01L 27/11556 (2017.01); H01L 27/1157 (2017.01); H01L 27/11573 (2017.01); G11C 8/10 (2006.01); H01L 21/02 (2006.01); H01L 27/11529 (2017.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); G11C 8/10 (2013.01); H01L 21/02164 (2013.01); H01L 21/02532 (2013.01); H01L 21/02595 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11529 (2013.01); H01L 27/11531 (2013.01); H01L 27/11556 (2013.01); H01L 27/11573 (2013.01); H01L 29/495 (2013.01); H01L 29/4966 (2013.01);
Abstract

Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments.


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