The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2023

Filed:

Jun. 21, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Han Hua Leong, Penang, MY;

Sita Rama Chandrasekhar Mallela, Bangalore, IN;

Muhammad Kazim Hafeez, Penang, MY;

Ming-Shiung Chen, Santa Clara, CA (US);

Anuj Agrawal, Fremont, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04J 3/06 (2006.01); G06F 11/16 (2006.01); H04L 43/106 (2022.01);
U.S. Cl.
CPC ...
H04J 3/0697 (2013.01); G06F 11/1679 (2013.01); H04J 3/0667 (2013.01); H04L 43/106 (2013.01);
Abstract

An integrated circuit has a transceiver circuit and a memory circuit. The transceiver circuit includes stage circuits that each perform at least one function specified by a data transmission protocol. The transceiver circuit is coupled to receive packets of timing test patterns. Each of the stage circuits in the transceiver circuit generates a timestamp in response to receiving each of the packets of timing test patterns. Each of the stage circuits in the transceiver circuit generates a trigger indicating receipt of a predefined reference point in each of the packets of timing test patterns. The memory circuit stores each of the timestamps generated by the stage circuits in response to a respective one of the triggers and outputs the timestamps for analysis.


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