The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2023

Filed:

Mar. 17, 2022
Applicant:

Quicklogic Corporation, San Jose, CA (US);

Inventors:

Ket Chong Yap, San Jose, CA (US);

Chihhung Liao, Fremont, CA (US);

Assignee:

QuickLogic Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/1776 (2020.01); H03K 19/17704 (2020.01); H03K 19/17736 (2020.01);
U.S. Cl.
CPC ...
H03K 19/1776 (2013.01); H03K 19/1774 (2013.01); H03K 19/17708 (2013.01); H03K 19/17744 (2013.01);
Abstract

A bit line (BL) may be coupled at a first end to a BL driver (BLD) and at a second end to a BL receiver (BLR). The BL include a plurality of sections and each BL section may be coupled to at least one corresponding sectional configuration memory latch controlled by: at least one sectional word line write (WLW-k) signal, which when asserted enables data to be written into the at least one corresponding sectional configuration memory latch when a corresponding tri-stateable sectional driver (SD-k) is activated, and at least one sectional word line read (WLR-k) signal, which when asserted enables data to be from the at least one corresponding sectional configuration memory latch when the corresponding sectional pull-up (PU-k) is activated.


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