The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2023

Filed:

Aug. 12, 2021
Applicant:

Ap Memory Technology Corp., Zhubei, TW;

Inventors:

Wen Liang Chen, Zhubei, TW;

Lin Ma, Zhubei, TW;

Chien-An Yu, Zhubei, TW;

Chun Yi Lin, Zhubei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/66 (2006.01); H01L 25/18 (2023.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 22/34 (2013.01); H01L 22/10 (2013.01); H01L 23/5226 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 25/18 (2013.01);
Abstract

A method to manufacture a semiconductor device includes: bonding a first wafer and a second wafer to be stacked vertically with one another, in which the first wafer provides a plurality of memory components and the second wafer provides a control circuit; forming a plurality of input/output channels on a surface of one of the first and second wafers; and cutting the bonded first and second wafers into a plurality of dices; wherein a plurality of first conductive contacts in the first wafer are electrically connected to the control circuit and the first conductive contacts in combinations with a plurality of first conductive vias in the first wafer form a plurality of transmission channels through which the control circuit is capable to access the memory components.


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