The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2023

Filed:

Apr. 26, 2021
Applicant:

Google Llc, Mountain View, CA (US);

Inventors:

Thomas Norrie, Mountain View, CA (US);

Naveen Kumar, San Jose, CA (US);

Assignee:

Google LLC, Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/30 (2006.01); G06F 16/48 (2019.01); G06F 11/34 (2006.01); G06F 9/54 (2006.01); G06F 11/36 (2006.01);
U.S. Cl.
CPC ...
G06F 11/302 (2013.01); G06F 9/542 (2013.01); G06F 11/3072 (2013.01); G06F 11/3075 (2013.01); G06F 11/3476 (2013.01); G06F 11/3495 (2013.01); G06F 11/3636 (2013.01); G06F 16/489 (2019.01); G06F 2201/86 (2013.01); G06F 2201/865 (2013.01);
Abstract

A computer-implemented method executed by one or more processors, the method includes monitoring execution of program code executed by a first processor component; and monitoring execution of program code executed by a second processor component. A computing system stores data identifying hardware events in a memory buffer. The stored events occur across processor units that include at least the first and second processor components. The hardware events each include an event time stamp and metadata characterizing the event. The system generates a data structure identifying the hardware events. The data structure arranges the events in a time ordered sequence and associates events with at least the first or second processor components. The system stores the data structure in a memory bank of a host device and uses the data structure to analyze performance of the program code executed by the first or second processor components.


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