The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2023

Filed:

Dec. 16, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Neha Bhargava, Bangalore, IN;

Arvindh Rajasekaran, Bangalore, IN;

Anup Deka, Bangalore, IN;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 19/25 (2006.01); H03K 5/24 (2006.01); G01R 31/40 (2020.01); H03K 21/08 (2006.01); H03M 1/66 (2006.01);
U.S. Cl.
CPC ...
G01R 19/25 (2013.01); G01R 31/40 (2013.01); H03K 5/24 (2013.01); H03K 21/08 (2013.01); H03M 1/66 (2013.01);
Abstract

A fast load current sensing apparatus and scheme provides instantaneous detection of peak current excursions using low silicon area and power efficient techniques. The response time for detecting signal excursions and measuring a signal (e.g., load current) is independent of resolution or precision and can be applied to high resolution telemetry. The apparatus sends out maximum current limit (FHC_limit) code at any instant the load current is detected to be more than a digital-to-analog converter (DAC) code. If the load current is less than the FHC_limit the scheme restores to a next DAC code as per a counter's next value. In case load current is more than FHC_limit, the scheme updates the DAC code to FHC_limit code and starts the counter from the FHC_limit.


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