The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 09, 2023
Filed:
Aug. 30, 2021
United Microelectronics Corp., Hsin-Chu, TW;
Hui-Lin Wang, Taipei, TW;
Yu-Ping Wang, Hsinchu, TW;
Chen-Yi Weng, New Taipei, TW;
Chin-Yang Hsieh, Tainan, TW;
Yi-Hui Lee, Taipei, TW;
Ying-Cheng Liu, Tainan, TW;
Yi-An Shih, Changhua County, TW;
I-Ming Tseng, Kaohsiung, TW;
Jing-Yin Jhang, Tainan, TW;
Chien-Ting Lin, Tainan, TW;
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Abstract
A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.