The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2023

Filed:

Dec. 31, 2020
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Bentian Jiang, Shatin, HK;

Natarajan Viswanathan, Austin, TX (US);

Zhuo Li, Austin, TX (US);

Yi-Xiao Ding, Austin, TX (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/3312 (2020.01); G06N 20/00 (2019.01); G06F 1/06 (2006.01);
U.S. Cl.
CPC ...
G06F 30/3312 (2020.01); G06F 1/06 (2013.01); G06N 20/00 (2019.01);
Abstract

Aspects of the present disclosure address systems and methods for performing a machine-learning based clustering of clock sinks during clock tree synthesis. An integrated circuit (IC) design comprising a clock net that includes a plurality of clock sinks is accessed. An initial number of clusters to generate from the set of clock sinks is determined using a machine-learning model. A first set of clusters is generated from the set of clocks sinks and includes the initial number of clusters. A timing analysis is performed to determine whether each cluster in the first set of clusters satisfies design rule constraints. The initial number of clusters is adjusted based on the timing analysis and a clustering solution is generated based on the adjusted number of clusters.


Find Patent Forward Citations

Loading…