The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2023

Filed:

Oct. 19, 2021
Applicant:

Rambus Inc., San Jose, CA (US);

Inventors:

Steven C. Woo, Saratoga, CA (US);

Thomas Vogelsang, Mountain View, CA (US);

Joseph James Tringali, Los Altos, CA (US);

Pooneh Safayenikoo, Columbia, MO (US);

Assignee:

Rambus Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 13/16 (2006.01); H01L 25/18 (2023.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
G06F 13/1668 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2225/06541 (2013.01);
Abstract

Processing elements include interfaces that allow direct access to memory banks on one or more DRAMs in an integrated circuit stack. These additional (e.g., per processing element) direct interfaces may allow the processing elements to have direct access to the data in the DRAM stack. Based on the size/type of operands being processed, and the memory bandwidth of the direct interfaces, rate calculation circuitry on the processor die determines the speed each processing element and/or processing nodes within each processing element are operated.


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