The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2023

Filed:

Jun. 27, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chin Yin, Tainan, TW;

Shang-Fu Yeh, Hsinchu, TW;

Calvin Yi-Ping Chao, Hsinchu County, TW;

Chih-Lin Lee, Miaoli County, TW;

Meng-Hsiu Wu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01S 7/48 (2006.01); G01S 7/4861 (2020.01); G01S 7/4865 (2020.01); G01S 17/10 (2020.01); H03L 7/089 (2006.01); H03L 7/081 (2006.01); G04F 10/00 (2006.01);
U.S. Cl.
CPC ...
G01S 7/4861 (2013.01); G01S 7/4865 (2013.01); G01S 17/10 (2013.01); G04F 10/005 (2013.01); H03L 7/0812 (2013.01); H03L 7/0891 (2013.01);
Abstract

A sensing device that is configured to determine a depth result based on time-of-flight value is introduced. The sensing device includes a delay locked loop circuit, a plurality of time-to-digital converters, a multiplexer and a digital integrator. The delay locked loop circuit is configured to output a plurality of delay clock signals through output terminals of the delay locked loop circuit. The plurality of time-to-digital converters include a plurality of latches. The multiplexer is configured to select a sub-group of m latches among the latches of the plurality of time-to-digital converters to be connected to the output terminals of the delay locked loop circuit according to a control signal. The digital integrator is coupled to the plurality of time-to-digital converters and is configured to integrate digital outputs generated by the time-to-digital converters in each of n cycles to generate n raw data frames, wherein m and n are natural numbers, and the n raw data frames are used to generate the depth result.


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