The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 02, 2023

Filed:

Mar. 22, 2021
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Christian Kasztelan, Munich, DE;

Alexander Breymesser, Villach, AT;

Manfred Mengel, Bad Abbach, DE;

Andreas Niederhofer, Regensburg, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 35/34 (2006.01); H01L 35/32 (2006.01); H01L 35/22 (2006.01); H01L 35/16 (2006.01);
U.S. Cl.
CPC ...
H01L 35/34 (2013.01); H01L 35/16 (2013.01); H01L 35/22 (2013.01); H01L 35/32 (2013.01);
Abstract

A method includes forming a plurality of first semiconductor mesa structures at a first semiconductor substrate. The first semiconductor substrate has a first conductivity type. The method further includes forming a plurality of second semiconductor mesa structures at a second semiconductor substrate. The second semiconductor substrate has a second conductivity type. The method further includes providing a glass substrate between the first semiconductor substrate and the second semiconductor substrate. The method includes connecting the first semiconductor substrate to the second semiconductor substrate so that at least a portion of the glass substrate is located laterally between the first semiconductor mesa structures of the plurality of first semiconductor mesa structures and the second semiconductor mesa structures of the plurality of second semiconductor mesa structures.


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