The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 02, 2023

Filed:

Aug. 15, 2019
Applicant:

Longitude Flash Memory Solutions Ltd., Dublin, IE;

Inventor:

Krishnaswamy Ramkumar, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11573 (2017.01); H01L 21/02 (2006.01); H01L 27/11568 (2017.01); H01L 21/28 (2006.01); H01L 27/1157 (2017.01); H01L 29/423 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11573 (2013.01); H01L 21/0223 (2013.01); H01L 27/1157 (2013.01); H01L 27/11568 (2013.01); H01L 29/40117 (2019.08); H01L 29/4234 (2013.01); H01L 21/31111 (2013.01); H01L 29/42364 (2013.01);
Abstract

Semiconductor devices and methods of manufacturing the same are provided. The semiconductor devices may have a non-volatile memory (NVM) transistor including a charge-trapping layer and a blocking dielectric, a field-effect transistor (FET) of a first type including a first gate dielectric having a first thickness, a FET of a second type including a second gate dielectric having a second thickness, and a FET of a third type including a third gate dielectric having a third thickness. In some embodiments, the first, second, and third gate dielectric includes a high dielectric constant (high-K) dielectric layer, and the first thickness is greater than the second thickness, the second thickness is greater than the third thickness. Other embodiments are also described.


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