The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 02, 2023
Filed:
Aug. 23, 2019
Intel Corporation, Santa Clara, CA (US);
Karl S. Papadantonakis, Agoura Hills, CA (US);
Robert Southworth, Chatsworth, CA (US);
Arvind Srinivasan, San Jose, CA (US);
Helia A. Naeimi, Santa Clara, CA (US);
James E. McCormick, Jr., Fort Collins, CO (US);
Jonathan Dama, Encino, CA (US);
Ramakrishna Huggahalli, Scottsdale, AZ (US);
Roberto Penaranda Cebrian, Santa Clara, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Examples are described herein that relate to a mesh in a switch fabric. The mesh can include one or more buses that permit operations (e.g., read, write, or responses) to continue in the same direction, drop off to a memory, drop off a bus to permit another operation to use the bus, or receive operations that are changing direction. A latency estimate can be determined at least for operations that drop off from a bus to permit another operation to use the bus or receive and channel operations that are changing direction. An operation with a highest latency estimate (e.g., time of traversing a mesh) can be permitted to use the bus, even causing another operation, that is not to change direction, to drop off the bus and re-enter later.