The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 02, 2023

Filed:

Oct. 19, 2021
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Evgueniy Nikolov Stefanov, Vieille Toulouse, FR;

Pascal Kamel Abouda, Saint Lys, FR;

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/13 (2006.01); H01L 49/02 (2006.01); H01L 27/08 (2006.01); H01L 23/522 (2006.01); H01L 29/94 (2006.01); H01L 27/06 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 27/13 (2013.01); H01L 23/5223 (2013.01); H01L 27/0805 (2013.01); H01L 28/40 (2013.01); H01L 28/87 (2013.01); H01L 28/90 (2013.01); H01L 29/94 (2013.01); H01L 29/945 (2013.01); H01L 27/067 (2013.01); H01L 27/0658 (2013.01); H01L 27/1203 (2013.01);
Abstract

There is disclosed herein an SOI IC comprising an integrated capacitor comprising a parallel arrangement of a metal-insulator-metal, MIM, capacitor, a second capacitor, a third capacitor, and a fourth capacitor: wherein the second capacitor comprises as plates the substrate and a one of a plurality of semiconductor layers having an n-type doping, and comprises the buried oxide layer as dielectric; the third capacitor comprises as plates the polysilicon layer and a further one of a plurality of semiconductor layers having an n-type doping, and comprises an insulating layer between the plurality of semiconductor layers and the metallisation stack as dielectric; andthe fourth capacitor comprises as plates the polysilicon plug and at least one of the plurality of semiconductor layers and comprises the oxide-lining as dielectric, wherein the oxide lining and the polysilicon plug form part of a lateral isolation (DTI) structure.


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