The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2023

Filed:

Sep. 30, 2021
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Badri Prasad Gopalan, Cupertino, CA (US);

Melvin Cardozo, San Jose, CA (US);

Deepesh Puthiya-Purayil, Dublin, CA (US);

Vamsi Krishna Doppalapudi, Hyberabad, IN;

Trinanjan Chatterjee, Bangalore, IN;

Yichun Wang, Shanghai, CN;

Assignee:

SYNOPSYS, INC., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/27 (2020.01); G06F 30/327 (2020.01); G06F 30/3308 (2020.01);
U.S. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 30/27 (2020.01); G06F 30/3308 (2020.01);
Abstract

Some aspects of this disclosure are directed automated performance tuning of a hardware description language (HDL) simulation system. For example, some aspects of this disclosure relate to a method, including generating, by a first subsystem optimizer, a plurality of recommendations corresponding to a first subsystem of a hardware description language (HDL) simulation system. The plurality of recommendations are generated by the first subsystem optimizer using one or more optimization applications. The method further includes generating, by the first subsystem optimizer, a first aggregate recommendation by combining the plurality of recommendations corresponding to the first subsystem of the HDL simulation system. The method further includes updating a configuration of the first subsystem of the HDL simulation system based on the first aggregate recommendation, wherein the HDL simulation system is configured to simulate a circuit design using the updated configuration during execution of the first subsystem.


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