The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2023

Filed:

Jan. 03, 2022
Applicant:

Globalfoundries U.s. Inc., Malta, NY (US);

Inventors:

Vivek Raj, Bangalore, IN;

Gregory A. Northrop, Everett, WA (US);

Shashank Nemawarkar, Austin, TX (US);

Shivraj Gurpadappa Dharne, Bangalore, IN;

Assignee:

GLOBALFOUNDRIES U.S. Inc., Malta, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 7/544 (2006.01);
U.S. Cl.
CPC ...
G06F 9/30029 (2013.01); G06F 9/3013 (2013.01); G06F 7/5443 (2013.01);
Abstract

Embodiments of the present disclosure provide a multi-port register file, including: a plurality of single-bit data registers for receiving and storing input data; a read path coupled to an output of each of the plurality of data registers; a plurality of AND gates, wherein an output of each of the plurality of data registers is coupled to an input of a respective AND gate of the plurality of AND gates; an input gating signal coupled to another input of each of the plurality of AND gates; a plurality of multi-bit registers, wherein an output of each of the plurality of AND gates is coupled to each of the plurality of multi-bit registers; and a write disable circuit coupled to the input gating signal for disabling a write signal applied to each of the plurality of multi-bit registers.


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