The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2023

Filed:

Oct. 18, 2021
Applicant:

Stmicroelectronics International N.v., Geneva, CH;

Inventors:

Rohit Goel, Patiala, IN;

Anand Kumar Mishra, Ghaziabad, IN;

Rajnish Garg, Noida, IN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3185 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318525 (2013.01); G01R 31/318552 (2013.01); G01R 31/318566 (2013.01); G01R 31/318594 (2013.01);
Abstract

An integrated circuit includes a data propagation path including a flip-flop. The flip-flop includes a first latch and a second latch. The integrated circuit includes a third latch that acts as a dummy latch. The input of the third latch is coupled to the output of the first latch. The integrated circuit includes a fault detector coupled to the output of the flip-flop and the output of the third latch. The third latch includes a signal propagation delay selected so that the third latch will fail to capture data in a given clock cycle before the second latch of the flip-flop fails to capture the data in the given clock cycle. The fault detector that detects when the third latch is failed to capture the data.


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