The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 18, 2023

Filed:

Apr. 25, 2022
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Sudipta Sarkar, San Jose, CA (US);

Dimitrios Loizos, Sunnyvale, CA (US);

Mehran Mohammadi Izad, San Diego, CA (US);

Paul Lee, San Francisco, CA (US);

Steven Elliott Mikes, Apex, NC (US);

Manohar Bhavsar Nagaraju, San Mateo, CA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 23/00 (2006.01); H03L 7/197 (2006.01); H03K 23/66 (2006.01); H03K 23/58 (2006.01); H03K 23/48 (2006.01);
U.S. Cl.
CPC ...
H03L 7/1974 (2013.01); H03K 23/486 (2013.01); H03K 23/58 (2013.01); H03K 23/66 (2013.01);
Abstract

Embodiments included herein are directed towards a fractional feedback divider circuit and associated method. The circuit may include a programmable feedback divider including a plurality of flip-flops arranged in series. The programmable feedback divider may be configured to receive an input clock signal and a reset signal comprising at least one pulse and to generate a divided clock. The circuit may include reset logic configured to receive an input from the programmable feedback divider and to generate a reset signal. The circuit may include a first D flip-flop configured to receive the reset signal and to generate an output and a second D flip-flop configured to receive the output from the first D flip-flop and to generate a second output. The circuit may further include a multiplexer configured to receive the second output and to generate an output clock signal.


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