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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11631470 B1

PDFFull Text
Date of Patent:
Apr. 18, 2023

Filed:

Jul. 30, 2021

Semiconductor chip, method of fabricating thereof, and method of testing a plurality of semiconductor chips

Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Szu Huat Goh, Singapore, SG;

Shaalini Sivaramakrishnan, Singapore, SG;

Li Song, Singapore, SG;

Wei Fong Soh, Singapore, SG;

Assignee:

GLOBALFOUNDRIES Singapore Pte. Ltd., Singapore, SG;

Attorney:

Viering Jentschura & Partner mbB

Primary Examiner:

Son L Mai

Int. Cl.
CPC ...
G11C 29/12 (2006.01); G11C 5/14 (2006.01); G11C 11/412 (2006.01); G11C 29/50 (2006.01);
U.S. Cl.
CPC ...
G11C 29/12005 (2013.01); G11C 5/14 (2013.01); G11C 11/4125 (2013.01); G11C 29/50004 (2013.01); G11C 2029/1202 (2013.01);
Abstract

A semiconductor chip may include a memory, a power supply line, a noise generator and a switch. The power supply line may include first and second power supply line portions. The power supply line may be configured to provide a power supply signal through each of the first power supply line portion and the second power supply line portion. The noise generator may be connected to the second power supply line portion. The noise generator may be configured to receive the power supply signal from the second power supply line portion, and output a noisy power supply signal based on the power supply signal. The switch may be coupled to the memory, the first power supply line portion, and the noise generator. The switch may be configured to selectively electrically connect the memory to one of the first power supply line portion and the noise generator.

Find Patent Forward Citations

Goh, Szu. (2023). Semiconductor chip, method of fabricating thereof, and method of testing a plurality of semiconductor chips (U.S. Patent No. 11631470). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11631470

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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