The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 18, 2023
Filed:
Nov. 04, 2019
Applicant:
Cadence Design Systems, Inc., San Jose, CA (US);
Inventors:
Stefano Lorenzini, Carnate, IT;
Antonino Armato, Bergamo, IT;
Assignee:
Cadence Design Systems, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 11/07 (2006.01); G05B 23/02 (2006.01); G06F 11/00 (2006.01); G06F 30/394 (2020.01); G06F 11/26 (2006.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G05B 23/0216 (2013.01); G06F 11/006 (2013.01); G06F 11/0712 (2013.01); G06F 11/261 (2013.01); G06F 30/394 (2020.01);
Abstract
Various embodiments provide for failure mode analysis of a circuit design, which can be used as part of electronic design automation (EDA). In particular, some embodiments provide for failure mode analysis of a circuit design by determining a set of functional primitives of a circuit design component (e.g., cell at gate level) that contribute to a root cause logic for a specific failure mode.