The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 18, 2023

Filed:

Jun. 29, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

David M. Durham, Beaverton, OR (US);

Michael Lemay, Hillsboro, OR (US);

Siddhartha Chhabra, Portland, OR (US);

Kai Cong, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/72 (2013.01); G06F 21/73 (2013.01); G06F 21/64 (2013.01); G06F 21/53 (2013.01); G06F 12/0895 (2016.01); H04L 9/06 (2006.01); H04L 9/00 (2022.01); H04L 9/32 (2006.01); G06F 21/75 (2013.01);
U.S. Cl.
CPC ...
G06F 21/72 (2013.01); G06F 12/0895 (2013.01); G06F 21/53 (2013.01); G06F 21/64 (2013.01); G06F 21/73 (2013.01); G06F 21/75 (2013.01); H04L 9/002 (2013.01); H04L 9/06 (2013.01); H04L 9/3236 (2013.01); G06F 2212/1052 (2013.01); H04L 2209/12 (2013.01);
Abstract

A system may use memory tagging for side-channel defense, memory safety, and sandboxing to reduce the likelihood of successful attacks. The system may include memory tagging circuitry to address existing and potential hardware and software architectures security vulnerabilities. The memory tagging circuitry may prevent memory pointers from being overwritten, prevent memory pointer manipulation (e.g., by adding values), and increase the granularity of memory tagging to include byte-level tagging in cache. The memory tagging circuitry may sandbox untrusted code by tagging portions of memory to indicate when the tagged portions of memory include contain a protected pointer. The memory tagging circuitry provides security features while enabling CPUs to continue using and benefiting from speculatively performing operations. By co-locating all tagging information at a cacheline granularity with its associated data, the processor has all the information needed to perform access control decisions immediately and non-speculatively, while maintaining high performance and cache coherency.


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