The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 11, 2023

Filed:

Jun. 14, 2022
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventor:

Shuai Guo, Hefei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10814 (2013.01); H01L 21/823412 (2013.01); H01L 21/823418 (2013.01); H01L 27/10823 (2013.01); H01L 27/10852 (2013.01); H01L 27/10855 (2013.01); H01L 27/10876 (2013.01); H01L 27/10885 (2013.01); H01L 29/4236 (2013.01); H01L 29/66742 (2013.01); H01L 29/78642 (2013.01); H01L 29/78696 (2013.01); H01L 27/10888 (2013.01);
Abstract

A memory device and a forming method thereof are provided. The memory device includes: a semiconductor substrate, wherein multiple active regions are formed in the semiconductor substrate, and the multiple active regions are separated by multiple first trenches extending along a first direction and multiple second trenches extending along a second direction; a third trench, extending along the first direction and located in the semiconductor substrate at the bottom of the first trench; a bit line doped region, located in the semiconductor substrate on two sides of the third trench; a gate dielectric layer, located on a sidewall surface of the first trench and a sidewall surface of the second trench; a first dielectric layer that fills the third trench; a metal gate, located in the second trench and the first trench on the first dielectric layer.


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