The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 11, 2023

Filed:

Sep. 01, 2020
Applicant:

Nichia Corporation, Anan, JP;

Inventors:

Haruhiko Nishikage, Anan, JP;

Yoshinori Miyamoto, Tokushima, JP;

Yasunobu Hosokawa, Tokushima, JP;

Assignee:

NICHIA CORPORATION, Anan, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/67 (2006.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/67092 (2013.01); H01L 21/78 (2013.01); H01L 2221/6834 (2013.01); H01L 2221/68372 (2013.01);
Abstract

A method for manufacturing a semiconductor element includes: providing a wafer comprising first and second regions at an upper surface of the wafer, the second region being located at a periphery of the first region and being at a lower position than the first region; and forming a semiconductor layer made of a nitride semiconductor at the upper surface of the wafer. In a top-view, the first region comprises an extension portion at an end portion of the first region in a first direction that passes through the center of the wafer parallel to an m-axis of the semiconductor layer, the extension portion extending in a direction from a center of the wafer toward an edge of the wafer or in a direction from an edge of the wafer toward a center of the wafer.


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