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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11625275 B1

PDFFull Text
Date of Patent:
Apr. 11, 2023

Filed:

Dec. 02, 2020

Technologies for controlling memory access transactions received from one or more i/o devices

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Krystof Zmudzinski, Forest Grove, OR (US);

Siddhartha Chhabra, Portland, OR (US);

Reshma Lal, Hillsboro, OR (US);

Alpa Narendra Trivedi, Portland, OR (US);

Luis S. Kida, Beaverton, OR (US);

Pradeep M. Pappachan, Tualatin, OR (US);

Abhishek Basak, Bothell, WA (US);

Anna Trikalinou, Hillsboro, OR (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:

Jaffery Watson Mendonsa & Hamilton LLP

Primary Examiner:

Tuan A Vu

Int. Cl.
CPC ...
G06F 9/445 (2018.01); G06F 9/50 (2006.01); G06F 9/455 (2018.01); G06F 21/62 (2013.01); G06F 12/1009 (2016.01); G06F 9/46 (2006.01); G06F 13/28 (2006.01); G06F 21/85 (2013.01); G06F 21/78 (2013.01); G06F 21/53 (2013.01); G06F 21/57 (2013.01); H04L 9/32 (2006.01); H04W 12/30 (2021.01); H04W 12/48 (2021.01); H04L 69/16 (2022.01);
U.S. Cl.
CPC ...
G06F 9/5016 (2013.01); G06F 9/45537 (2013.01); G06F 9/45545 (2013.01); G06F 9/45558 (2013.01); G06F 9/466 (2013.01); G06F 12/1009 (2013.01); G06F 13/28 (2013.01); G06F 21/53 (2013.01); G06F 21/57 (2013.01); G06F 21/62 (2013.01); G06F 21/78 (2013.01); G06F 21/85 (2013.01); H04L 9/3234 (2013.01); H04L 9/3263 (2013.01); G06F 2009/45583 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/7201 (2013.01); H04L 9/3242 (2013.01); H04L 69/162 (2013.01); H04L 2209/127 (2013.01); H04W 12/30 (2021.01); H04W 12/48 (2021.01);
Abstract

Technologies for secure I/O include a compute device, which further includes a processor, a memory, a trusted execution environment (TEE), one or more input/output (I/O) devices, and an I/O subsystem. The I/O subsystem includes a device memory access table (DMAT) programmed by the TEE to establish bindings between the TEE and one or more I/O devices that the TEE trusts and a memory ownership table (MOT) programmed by the TEE when a memory page is allocated to the TEE.

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