The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 11, 2023
Filed:
Sep. 28, 2018
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Eriko Nurvitadhi, Hillsboro, OR (US);
Scott J. Weber, Piedmont, CA (US);
Ravi Prakash Gutala, San Jose, CA (US);
Aravind Raghavendra Dasu, Milpitas, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G05B 19/05 (2006.01); G06N 3/02 (2006.01); G06F 15/78 (2006.01); G06F 30/34 (2020.01); G06F 30/39 (2020.01);
U.S. Cl.
CPC ...
G06F 9/30036 (2013.01); G05B 19/056 (2013.01); G06F 9/3001 (2013.01); G06F 9/3004 (2013.01); G06F 15/7821 (2013.01); G06F 30/34 (2020.01); G06F 30/39 (2020.01); G06N 3/02 (2013.01); G05B 2219/21109 (2013.01);
Abstract
An integrated circuit device may include programmable logic circuitry on a first integrated circuit die and memory that includes compute-in-memory circuitry on a second die. The programmable logic circuitry may be programmed with a circuit design that operates on a first set of data. The compute-in-memory circuitry of the memory may perform an arithmetic operation using the first set of data from the programmable logic circuitry and a second set of data stored in the memory.