The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2023

Filed:

Jun. 12, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Ta-Pen Guo, Taipei, TW;

Chi-Lin Liu, New Taipei, TW;

Shang-Chih Hsieh, Yangmei, TW;

Jerry Chang-Jui Kao, Taipei, TW;

Li-Chun Tien, Tainan, TW;

Lee-Chung Lu, Taipei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01); H03K 3/0233 (2006.01); H03K 23/58 (2006.01); H03K 19/094 (2006.01); H03K 3/01 (2006.01); H01L 27/02 (2006.01); H03K 3/356 (2006.01); H03K 3/3562 (2006.01); H01L 27/118 (2006.01); H01L 27/092 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H03K 3/02332 (2013.01); H01L 27/0207 (2013.01); H01L 27/0233 (2013.01); H01L 27/0924 (2013.01); H01L 27/11807 (2013.01); H03K 3/01 (2013.01); H03K 3/35625 (2013.01); H03K 3/356121 (2013.01); H03K 19/094 (2013.01); H03K 23/58 (2013.01); H01L 27/1211 (2013.01); H01L 2027/11875 (2013.01); H01L 2027/11879 (2013.01);
Abstract

A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.


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