The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2023

Filed:

Aug. 05, 2021
Applicant:

Wolfspeed, Inc., Durham, NC (US);

Inventors:

Young-Youl Song, Gilroy, CA (US);

Zulhazmi A. Mokhti, Morgan Hill, CA (US);

John Wood, Raleigh, NC (US);

Qianli Mu, San Jose, CA (US);

Jeremy Fisher, Raleigh, NC (US);

Assignee:

Wolfspeed, Inc., Durham, NC (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 1/30 (2006.01); H03F 1/02 (2006.01); H01L 29/778 (2006.01); H01L 29/20 (2006.01); H01L 23/66 (2006.01); H03F 3/213 (2006.01); H03F 3/195 (2006.01); H03F 1/32 (2006.01);
U.S. Cl.
CPC ...
H03F 1/0222 (2013.01); H01L 23/66 (2013.01); H01L 29/2003 (2013.01); H01L 29/7787 (2013.01); H03F 1/3205 (2013.01); H03F 3/195 (2013.01); H03F 3/213 (2013.01); H01L 2223/665 (2013.01); H01L 2223/6655 (2013.01); H01L 2223/6683 (2013.01); H03F 1/0288 (2013.01); H03F 2200/451 (2013.01); H03F 2200/462 (2013.01);
Abstract

A circuit includes a field effect transistor (FET), a reference transistor having an output coupled to an output of the FET, an active bias circuit coupled to the reference transistor and configured to generate an input signal for the reference transistor in response to a change in drain current of the reference transistor due to carrier trapping and to apply the input signal to an input of the reference transistor, and a summing node coupled to an input of the FET and to the input of the reference transistor. The summing node adds the input signal to an input signal of the FET to compensate the carrier trapping effect.


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