The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2023

Filed:

Sep. 10, 2020
Applicant:

Semiconductor Components Industries, Llc, Phoenix, AZ (US);

Inventors:

Gary Horst Loechelt, Tempe, AZ (US);

Balaji Padmanabhan, Chandler, AZ (US);

Dean E. Probst, West Jordan, UT (US);

Tirthajyoti Sarkar, Fremont, CA (US);

Prasad Venkatraman, Gilbert, AZ (US);

Muh-Ling Ger, Chandler, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 23/528 (2006.01); H01L 29/739 (2006.01); H01L 29/10 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/407 (2013.01); H01L 23/5286 (2013.01); H01L 29/0634 (2013.01); H01L 29/1095 (2013.01); H01L 29/7397 (2013.01);
Abstract

A circuit and physical structure can help to counteract non-linear Cassociated with power transistors that operate at higher switching speeds and lower R. In an embodiment, a component with a pn junction can be coupled to an n-channel IGFET. The component can include a p-channel IGFET, a pnp bipolar transistor, or both. A gate/capacitor electrode can be within a trench that is adjacent to the active regions of the component and n-channel IGFET, where the active regions can be within a semiconductor pillar. The combination of a conductive member and the semiconductor pillar of the component can be a charge storage component. The physical structure may include a compensation region, a barrier doped region, or both. In a particular embodiment, doped surface regions can be coupled to a buried conductive region without the use of a topside interconnect or a deep collector type of structure.


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