The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2023

Filed:

Feb. 17, 2021
Applicant:

Tokyo Electron Limited, Tokyo, JP;

Inventors:

Rintaro Takao, Hokkaido, JP;

Naohide Ito, Iwate, JP;

Hiroaki Dewa, Hokkaido, JP;

Masayuki Kozawa, Hokkaido, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/677 (2006.01); H01L 21/68 (2006.01); B65G 49/07 (2006.01); H01L 21/67 (2006.01); G05B 19/418 (2006.01);
U.S. Cl.
CPC ...
H01L 21/6773 (2013.01); B65G 49/07 (2013.01); G05B 19/41865 (2013.01); H01L 21/67276 (2013.01); H01L 21/68 (2013.01); G05B 2219/2602 (2013.01); G05B 2219/45031 (2013.01); G05B 2219/45032 (2013.01);
Abstract

A semiconductor manufacturing apparatus includes one or more process modules, a scheduler, and a transfer controller. A product wafer of a lot that is transferred from a load port to one of the one or more process modules is replenished such that a total number of wafers that are simultaneously processed in the one or more process modules becomes N. When an advance lot being processed and a post lot to be processed subsequent to the advance lot have a same processing condition, the scheduler creates the transfer plan to replenish with the product wafer of the post lot instead of a dummy wafer such that the transfer controller transfers the product wafer and the dummy wafer to the one or more process modules according to the created transfer plan.


Find Patent Forward Citations

Loading…