The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2023

Filed:

Jul. 30, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Udaya Shankar Natarajan, El Dorado Hills, CA (US);

Kannappan Rajaraman, Bangalore, IN;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02J 7/00 (2006.01); G06F 1/26 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
H02J 7/00047 (2020.01); G06F 1/26 (2013.01); G06F 13/4282 (2013.01); H02J 7/00036 (2020.01); H02J 7/0068 (2013.01);
Abstract

A software and hardware architecture framework utilize the specifications of Universal Serial Bus (USB) Type-C and Power Deliver (PD) to provide fine grain throttling of a processor (e.g., system-on-chip (SoC)). Based on an external charger connection or disconnection, a low latency fine grain power budget loss or gain indication to the processor is delivered. The mechanism of various embodiments is also applicable to connection or disconnection of VBUS powered peripheral devices to the system. The net power loss or gain available to the SoC and System is proportionally used to scale the processor throttling.


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