The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2023

Filed:

Jun. 14, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Chang Hwan Choi, Seoul, KR;

Yun Heub Song, Seongnam-si, KR;

Bon Cheol Ku, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11597 (2017.01); H01L 27/1159 (2017.01); H01L 21/02 (2006.01); H01L 29/51 (2006.01); H01L 21/28 (2006.01); H01L 29/24 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11597 (2013.01); H01L 21/02565 (2013.01); H01L 27/1159 (2013.01); H01L 29/24 (2013.01); H01L 29/40111 (2019.08); H01L 29/516 (2013.01);
Abstract

Disclosed is a method of manufacturing a three-dimensional semiconductor memory device including a ferroelectric thin film. The method includes forming a mold structure including interlayer dielectric layers and sacrificial layers alternately stacked on a substrate, forming channel holes penetrating the mold structure, forming vertical channel structures inside the channel holes, forming an isolation trench penetrating the mold structure and having a line shape extending in one direction, selectively removing the sacrificial layers exposed by the isolation trench, forming gate electrodes filling a space from which the sacrificial layers are removed, and performing a heat treatment process and a cooling process for the vertical channel structures.


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