The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2023

Filed:

Sep. 04, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventor:

Chih-Yu Wang, Taichung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/308 (2006.01); H01L 21/311 (2006.01); H01L 27/092 (2006.01); H01L 29/78 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3086 (2013.01); H01L 21/3081 (2013.01); H01L 21/31116 (2013.01); H01L 21/823821 (2013.01); H01L 27/0924 (2013.01); H01L 29/7853 (2013.01);
Abstract

A method includes depositing a mask layer over a semiconductor substrate, etching the mask layer to form a patterned mask, wherein a sidewall of the patterned mask includes a first sidewall region, a second sidewall region, and a third sidewall region, wherein the first sidewall region is farther from the semiconductor substrate than the second sidewall region and the second sidewall region is farther from the semiconductor substrate than the third sidewall region, wherein the second sidewall region protrudes laterally from the first sidewall region and from the third sidewall region, etching the semiconductor substrate using the patterned mask to form fins, forming a gate stack over the fins, and forming source and drain regions in the fin adjacent the gate stack.


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