The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2023

Filed:

Aug. 18, 2021
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Jurgen Geerlings, Suzhou, CN;

Glenn Charles Abeln, Buda, TX (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 (2006.01); G11C 11/417 (2006.01);
U.S. Cl.
CPC ...
G11C 11/417 (2013.01); G11C 5/147 (2013.01);
Abstract

An integrated circuit (IC) includes a plurality of volatile memory (VM) blocks, and a power gate control circuit configured to control power gating for each VM block of a plurality of VM blocks. The IC includes a power mode controller circuit configured to select a power mode, and in response to selecting a retention mode as the power mode, the power mode controller circuit gates a supply voltage from each block of a selected subset of the plurality of VM blocks and allows a retention voltage to power each VM block of a remaining subset of the plurality of VM blocks outside the selected subset. The IC includes a voltage controller circuit configured to determine a voltage level of the retention voltage based on a minimum retention voltage required for each VM block of the remaining subset.


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