The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 28, 2023
Filed:
Sep. 16, 2020
Methods and apparatus for organizing a programmable semiconductor device into multiple clock regions
Gowin Semiconductor Corporation, GuangZhou, CN;
Jianhua Liu, Fremont, CA (US);
Jinghui Zhu, San Jose, CA (US);
Ning Song, Cupertino, CA (US);
Tianping Wang, Shanghai, CN;
Chienkuang Chen, Santa Clara, CA (US);
Diwakar Chopperla, Fremont, CA (US);
Tianxin Wang, Shanghai, CN;
Zhenyu Gu, Shanghai, CN;
Xiaozhi Lin, Shanghai, CN;
GOWIN SEMICONDUCTOR CORPORATION, Guangzhou, CN;
Abstract
A configurable semiconductor device ('CSD') is organized in four (4) quadrants able to perform user-defined logic functions via a clock fabric. The first quadrant, in one embodiment, includes a first serializer and deserializer ('SerDes') region and a bank0 region for data processing. The second quadrant includes a second SerDes region and a bank5 region and the third quadrant contains a bank3 region and a bank4 region. The fourth quadrant includes a bank1 region and a bank2 region. The clock fabric is configured to provide a set of programmable or selectable clock signals with different clock speeds to various regions within the CSD.