The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 21, 2023
Filed:
Jul. 02, 2021
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Xiao Chen, San Diego, CA (US);
Chen-ju Hsieh, Campbell, CA (US);
Sung Son, San Jose, CA (US);
Chulmin Jung, San Diego, CA (US);
Assignee:
QUALCOMM, INCORPORATED, San Diego, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/00 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 17/12 (2006.01); G11C 16/08 (2006.01); G11C 16/04 (2006.01); G11C 16/24 (2006.01);
U.S. Cl.
CPC ...
G11C 16/102 (2013.01); G11C 16/0433 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 17/126 (2013.01);
Abstract
A drain programmed read-only memory includes a diffusion region that spans a width of a bitcell and forms a drain of a first transistor and a second transistor. A bit line lead in a metal layer adjacent the diffusion region extends across the width of the bitcell. A first via extends from an upper half of the bit line lead and couples to a drain of the first transistor. Similarly, a second via extends from a lower half of the bit line and couples to a drain of the second transistor.