The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2023

Filed:

Nov. 23, 2020
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Joshua S. Holt, Santa Clara, CA (US);

Lan Yu, Albany, NY (US);

Tyler Sherwood, Fonda, NY (US);

Archana Kumar, Mountain View, CA (US);

Nicolas Louis Gabriel Breil, Alviso, CA (US);

Siddarth Krishnan, San Jose, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/872 (2006.01); H01L 21/28 (2006.01); H01L 29/45 (2006.01); H01L 29/861 (2006.01); H01L 29/66 (2006.01); H01L 29/47 (2006.01);
U.S. Cl.
CPC ...
H01L 29/872 (2013.01); H01L 21/28052 (2013.01); H01L 29/456 (2013.01); H01L 29/47 (2013.01); H01L 29/6609 (2013.01); H01L 29/66143 (2013.01); H01L 29/861 (2013.01);
Abstract

Exemplary methods of forming a semiconductor structure may include forming a layer of metal on a semiconductor substrate. The layer of metal may extend along a first surface of the semiconductor substrate. The semiconductor substrate may be or include silicon. The methods may include performing an anneal to produce a metal silicide. The methods may include implanting ions in the metal silicide to increase a barrier height over 0.65 V.


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