The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2023

Filed:

Nov. 05, 2021
Applicant:

Nanya Technology Corporation, New Taipei, TW;

Inventor:

Chun-Heng Wu, Taoyuan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 27/108 (2006.01); H01L 23/535 (2006.01); H01L 23/485 (2006.01); H01L 23/532 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76829 (2013.01); H01L 23/485 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/535 (2013.01); H01L 23/53295 (2013.01); H01L 27/10808 (2013.01); H01L 27/10855 (2013.01);
Abstract

A for preparing a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, and forming an etch stop layer over the first dielectric layer. The method also includes forming a second dielectric layer over the etch stop layer, and forming a first metal plug penetrating through the second dielectric layer, the etch stop layer and the first dielectric layer. The first metal plug protrudes from the second dielectric layer. The method further includes performing an anisotropic etching process to partially remove the first metal plug such that the first metal plug has a convex top surface, and forming a third dielectric layer covering the second dielectric layer and the convex top surface of the first metal plug. In addition, the method includes forming a second metal plug over the first metal plug.


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