The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2023

Filed:

Sep. 10, 2021
Applicant:

Ememory Technology Inc., Hsinchu, TW;

Inventor:

Ting-Ting Su, Hsinchu County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); H01L 27/11519 (2017.01); H01L 29/423 (2006.01); H01L 29/788 (2006.01); H01L 27/11521 (2017.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3477 (2013.01); H01L 27/11519 (2013.01); H01L 27/11521 (2013.01); H01L 29/42328 (2013.01); H01L 29/788 (2013.01); G11C 16/0433 (2013.01);
Abstract

Provided is a memory device including a memory structure including a substrate, a channel region, first and second doped regions, a floating gate and a dielectric layer. The channel region is disposed on the substrate. The first and the second doped regions are disposed on the substrate and respectively located at two sides of the channel region. The floating gate is disposed on the channel region. The dielectric layer is disposed between the floating gate and the channel region, the first doped region and the second doped region. The floating gate and the first doped region are partially overlapped, and/or the floating gate and the second doped region are not overlapped and a sidewall of the floating gate adjacent to the second doped region and a boundary between the second doped region and the channel region are separated by a distance.


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