The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2023

Filed:

Mar. 02, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jongyoun Kim, Seoul, KR;

Seokhyun Lee, Hwaseong-si, KR;

Minjun Bae, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/528 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 21/565 (2013.01); H01L 21/76819 (2013.01); H01L 21/76871 (2013.01); H01L 21/76877 (2013.01); H01L 23/3128 (2013.01); H01L 23/5283 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/02373 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/0401 (2013.01);
Abstract

A method is provided and includes forming a first conductive pattern; forming a photosensitive layer on the first conductive pattern, the photosensitive layer having a first through hole exposing a portion of the first conductive pattern; forming a first via in the first through hole; removing the photosensitive layer; forming a dielectric layer encapsulating the first conductive pattern and the first via, the dielectric layer exposing a top surface of the first via; forming a second conductive pattern on the top surface of the first via, forming a dielectric layer covering the second conductive pattern; etching the dielectric layer to form a second through hole that exposes a portion of the second conductive pattern; forming a second via filling the second through hole and an under bump pad on the second via; and mounting a semiconductor chip on the under bump pad using a connection terminal.


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