The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2023

Filed:

Jul. 29, 2021
Applicant:

Shanghai Huali Microelectronics Corporation, Shanghai, CN;

Inventors:

Pengkai Xu, Shanghai, CN;

Fulong Qiao, Shanghai, CN;

Wenyan Sun, Shanghai, CN;

Yu Huang, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/3105 (2006.01); H01L 21/311 (2006.01); H01L 27/11531 (2017.01); H01L 27/11524 (2017.01);
U.S. Cl.
CPC ...
H01L 21/31053 (2013.01); H01L 21/31051 (2013.01); H01L 21/31111 (2013.01); H01L 27/11531 (2013.01); H01L 27/11524 (2013.01);
Abstract

The present disclosure provides a method for manufacturing a semiconductor device, including: providing a substrate having a plurality of stacked gates with silicon nitride mask layer and silicon oxide mask layer formed on top of the surface; depositing a first carbon-containing silicon oxide thin layer; depositing a second non-carbon-containing silicon oxide layer to fill the gaps between adjacent stacked gates; and planarizing the first silicon oxide thin layer and the second silicon oxide layer by applying the silicon nitride mask layer as a stop layer, removing the second silicon oxide layer, and forming the first sidewalls with the first silicon oxide thin layer on the sides of the stacked gates. The present disclosure further provides a semiconductor device made with the method thereof. The present disclosure can remove the silicon oxide mask layer above the stacked gates through a simple process flow.


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