The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2023

Filed:

Jul. 22, 2020
Applicant:

Diakopto, Inc., San Jose, CA (US);

Inventor:

Maxim Ershov, San Jose, CA (US);

Assignee:

Diakopto, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/398 (2020.01); G06F 111/20 (2020.01); G06F 111/04 (2020.01);
U.S. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/398 (2020.01); G06F 2111/04 (2020.01); G06F 2111/20 (2020.01);
Abstract

A computer/software tool for electronic design automation (EDA) extracts parasitics from a post-layout netlist file for an integrated circuit (IC) design and uses these parasitics to model circuit behavior between one or more excitation points and one or more observation points for a given circuit design characteristic. Sensitivities of that given circuit design characteristic to each constituent parasitic (or a group of parasitics that might be, for example, associated with a given structural element such as a layer) are then computed. The computer/software tool generates a visual display based on the relative sensitivities; for example, in one embodiment, relative sensitivities can be color-coded to permit a designer to visualize sources of problems in the IC design. In other embodiments, the sensitivities can be filtered and/or processed, e.g., so as to provide EDA driven assistance to changes to reduce excessive sensitivities or sensitivities to certain parasitics.


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