The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2023

Filed:

Dec. 05, 2019
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Ivan Nikitin, Regensburg, DE;

Dirk Ahlers, Munich, DE;

Andreas Grassmann, Regensburg, DE;

Andre Uhlemann, Wickede, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02B 1/118 (2015.01); H05K 3/40 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H05K 1/05 (2006.01); H01L 23/28 (2006.01); H05K 1/18 (2006.01); H05K 1/02 (2006.01); H05K 3/00 (2006.01);
U.S. Cl.
CPC ...
G02B 1/118 (2013.01); H01L 23/28 (2013.01); H01L 23/31 (2013.01); H01L 24/83 (2013.01); H05K 1/0204 (2013.01); H05K 1/053 (2013.01); H05K 1/185 (2013.01); H05K 3/0061 (2013.01); H05K 3/40 (2013.01);
Abstract

A power semiconductor module includes a first substrate, wherein the first substrate includes aluminum, a first aluminum oxide layer arranged on the first substrate, a conductive layer arranged on the first aluminum oxide layer, a first semiconductor chip, wherein the first semiconductor chip is arranged on the conductive layer and is electrically connected thereto, and an electrical insulation material enclosing the first semiconductor chip, wherein the first aluminum oxide layer is configured to electrically insulate the first semiconductor chip from the first substrate.


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