The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2023

Filed:

Apr. 29, 2020
Applicant:

Ferroelectric Memory Gmbh, Dresden, DE;

Inventors:

Marko Noack, Dresden, DE;

Rolf Jähne, Dresden, DE;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/22 (2006.01); G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
G11C 11/2259 (2013.01); G11C 5/06 (2013.01); G11C 11/2253 (2013.01); G11C 11/2273 (2013.01); G11C 11/2275 (2013.01); G11C 11/2297 (2013.01);
Abstract

In various embodiments, a memory cell arrangement is provided including a memory cell driver and one or more memory cells, wherein one or more control nodes of each of the one or more memory cells are electrically conductively connected to one or more output nodes of the memory cell driver. The memory cell driver may include: a first supply node to receive a first supply voltage and a second supply node to receive a second supply voltage, a plurality of input nodes to receive a plurality of input voltages, one or more output nodes, and a logic circuit connected to the first supply node, the second supply node, the plurality of input nodes, and the one or more output nodes, wherein the logic circuit includes one or more logic gates and is configured to connect via the one or more logic gates either the first supply node or the second supply node to the one or more output nodes in response to the plurality of input voltages.


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