The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2023

Filed:

May. 31, 2021
Applicant:

Redpine Signals, Inc., San Jose, CA (US);

Inventors:

Martin Kraemer, Mountain View, CA (US);

Ryan Boesch, Louisville, CO (US);

Wei Xiong, Mountain View, CA (US);

Assignee:

Ceremorphic, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06J 1/00 (2006.01); H03K 19/20 (2006.01); H03M 1/38 (2006.01); H03M 3/04 (2006.01);
U.S. Cl.
CPC ...
G06J 1/00 (2013.01); H03K 19/20 (2013.01); H03M 1/38 (2013.01); H03M 3/04 (2013.01);
Abstract

A Unit Element (UE) has a positive UE and a negative UE, each having a digital X input and a digital W input with a sign bit, the sign bit is exclusive ORed with a chop clock to generate a chopped sign bit. The positive UE is enabled when the chopped sign bit is positive and the negative UE is enabled when the chopped sign bit is negative. Each positive and negative UE comprises groups of NAND gates generating an output and complementary output which are coupled to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The NAND gate outputs and complementary outputs are coupled through binary weighted charge transfer capacitors the positive charge transfer line and negative charge transfer line.


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