The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2023

Filed:

Dec. 02, 2021
Applicant:

Power Integrations, Inc., San Jose, CA (US);

Inventor:

Akshay Nayaknur, Sunnyvale, CA (US);

Assignee:

POWER INTEGRATIONS, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 3/335 (2006.01); H02M 1/00 (2006.01); H02M 1/08 (2006.01);
U.S. Cl.
CPC ...
H02M 3/33592 (2013.01); H02M 1/0012 (2021.05); H02M 1/083 (2013.01);
Abstract

An input voltage estimate circuit for use in a power converter. The input voltage estimate circuit comprises a timer, which comprises a timer control circuit to generate a control signal in response to a request signal, a winding signal, and an output voltage signal. The control signal is coupled to transition to a first logic level in response to a request event in the request signal, and to transition to a second logic level in response to the winding signal falling below the output voltage signal. The timer comprises a primary conduction timer to generate a primary conduction time signal in response to the first logic level and the second logic level in the control signal and a secondary conduction timer to generate a secondary conduction time signal in response to the second logic level in the control signal and a second logic level in a second drive signal.


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