The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2023

Filed:

Nov. 19, 2021
Applicant:

Advantest Test Solutions, Inc., San Jose, CA (US);

Inventors:

Karthik Ranganathan, Foothill Ranch, CA (US);

Gregory Cruzan, Anaheim, CA (US);

Samer Kabbani, Laguna Niguel, CA (US);

Gilberto Oseguera, Corona, CA (US);

Ira Leventhal, San Jose, CA (US);

Assignee:

Advantest Test Solutions, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/319 (2006.01); G11C 29/56 (2006.01); G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
G11C 29/56016 (2013.01); G01R 31/2863 (2013.01); G01R 31/2867 (2013.01); G01R 31/31905 (2013.01); G11C 2029/5602 (2013.01);
Abstract

A testing apparatus comprises a tester comprising a plurality of racks, wherein each rack comprises a plurality of slots, wherein each slot comprises: (a) an interface board affixed in a slot of a rack, wherein the interface board comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT); and (b) a carrier comprising an array of DUTs, wherein the carrier is operable to displace into the slot of the rack; and (c) an array of POP memory devices, wherein each POP memory device is disposed adjacent to a respective DUT in the array of DUTs. Further, the testing apparatus comprises a pick-and-place mechanism for loading the array of DUTs into the carrier and an elevator for transporting the carrier to the slot of the rack.


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